Field of the Invention
The invention relates to a delay circuit for digital signals having an adjustable delay time, including a series circuit disposed between two supply potentials. The series circuit includes controlled paths at least of a first transistor of a first conduction type and second and third transistors of a second conduction type. Control connections of the first and second transistors are connected to a signal input of the delay circuit. One connection of the first transistor, which is remote from the first supply potential, is connected to a signal output of the delay circuit. A fourth transistor is connected in parallel with the third transistor and is of the second conduction type. A first control input is connected to a control connection of the third transistor, and a second control input is connected to a control connection of the fourth transistor. The control inputs are used to adjust a delay time of the delay circuit.
Such a circuit is disclosed in European Patent Application 0 647 025 A1. However, a disadvantage of that circuit is that, when all of the parallel-connected transistors used to adjust the delay time are turned off, the output of the delay circuit floats, that is to say it is not at a fixed potential, so that under some circumstances circuit units connected downstream of the delay circuit are supplied with an undefined potential.